D a t a
S h e e t
Erase and Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Word Programming Time
Chip Programming Time
(Note 3)
Byte Mode
Word Mode
Typ (Note 1)
0.7
32
18
18
36
19
Max (Note 2)
7.5
Unit
s
s
µs
µs
s
s
Excludes system level
overhead (Note 5)
Comments
Excludes 00h programming
prior to erasure (Note 4)
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, V
CC
= 3.0 V, 10,000 cycles, checkerboard data
pattern.
2. Under worst case conditions of 90°C, V
CC
= 2.7 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Tables
2–3
for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol
C
IN
C
OUT
C
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter Description
Input Capacitance
Output Capacitance
Control Pin Capacitance
Test Setup
V
IN
= 0
V
OUT
= 0
V
IN
= 0
TSOP
BGA
TSOP
BGA
TSOP
BGA
Typ
6
4.2
8.5
5.4
7.5
3.9
Max
7.5
5.0
12
6.5
9
4.7
Unit
pF
pF
pF
pF
pF
pF
October 11, 2006 S29AL016M_00_A7
S29AL016M
53
SPANSION [ SPANSION ]
