A d v a n c e I n f o r m a t i o n
the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
CC
0.3 V. (Note that this is a more restricted voltage range than V .) If CE# and RESET# are held
IH
at V , but not within V
0.3 V, the device will be in the standby mode, but the standby current
IH
CC
will be greater. The device requires standard access time (t ) for read access when the device is
CE
in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
In the DC Characteristics table, I
and I
represents the standby current specification.
CC4
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for t + 30 ns. The automatic sleep mode is
ACC
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. I
in DC Characteristics on page 46 represents the automatic sleep
CC4
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When
the system drives the RESET# pin to V for at least a period of t , the device immediately ter-
IL
RP
minates any operation in progress, tristates all data output pins, and ignores all read/write
attempts for the duration of the RESET# pulse. The device also resets the internal state machine
to reading array data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V ±0.3 V, the
SS
device draws CMOS standby current (I
standby current will be greater.
). If RESET# is held at V but not within V ±0.3 V, the
IL SS
CC4
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy)
until the internal reset operation is complete, which requires a time of t
(during Embedded
READY
Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is
complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin
is 1), the reset operation is completed within a time of t
(not during Embedded Algorithms).
READY
The system can read data t
after the RESET# pin returns to V .
IH
RH
Refer to AC Characteristics on page 50 for RESET# parameters and to Figure 15, on page 51 for
the timing diagram.
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The output pins are placed in
IH
the high impedance state.
June 13, 2005 S29AL032D_00_A3
S29AL032D
13
SPANSION [ SPANSION ]
