A d v a n c e I n f o r m a t i o n
the Embedded Program algorithm. The system is not required to provide further controls or tim-
ings. The device automatically generates the program pulses and verifies the programmed cell
margin. Table 17 on page 38 shows the address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array
data and addresses are no longer latched. The system can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 39 for information
on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates the programming operation. The Byte Program
command sequence should be reinitiated once the device has reset to reading array data, to en-
sure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
grammed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1,
or cause the Data# Polling algorithm to indicate the operation was successful. However, a suc-
ceeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than
using the standard program command sequence. The unlock bypass command sequence is initi-
ated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock
bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second cycle contains
the program address and data. Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table 17 on page 38 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 4, on page 34 illustrates the algorithm for the program operation. See the Erase/Program
Operations on page 54 for parameters, and to Figure 18, on page 55 for timing diagrams.
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