D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
12. Appendix
This section contains information relating to software control or interfacing with the Flash device. For
additional information and assistance regarding software, see Section 5. For the latest information, explore
the Spansion web site at www.spansion.com.
12.1 Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Tables 12.1–12.4 define the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence can place the device in an unknown state. A reset
command is then required to return the device to reading array data.
Table 12.1 S29GL-P Memory Array Command Definitions, x16
Bus Cycles (Notes 1–5)
First
Addr
Second
Third
Fourth
Fifth
Addr
Sixth
Command (Notes)
Data
RD
F0
Addr
Data
Addr
Data
Addr
Data
Data
Addr
Data
Read (6)
Reset (7)
1
1
4
4
4
RA
XXX
555
555
555
Manufacturer ID
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
90
90
90
X00
X01
01
Device ID (8)
227E
(10)
X0E
(8)
X0F
(8)
Sector Protect Verify (10)
[SA]X02
Secure Device Verify (11)
4
555
AA
2AA
55
555
90
X03
(11)
CFI Query (12)
1
4
3
1
3
3
2
2
2
2
6
6
1
1
3
4
55
98
AA
AA
29
Program
555
555
SA
2AA
2AA
55
55
555
SA
A0
25
PA
SA
PD
Write to Buffer
WC
WBL
PD
WBL
PD
Program Buffer to Flash (Confirm)
Write-to-Buffer-Abort Reset (13)
Enter
555
555
XXX
XXX
XXX
XXX
555
555
XXX
XXX
555
555
AA
AA
A0
80
2AA
2AA
PA
55
55
PD
30
10
00
55
55
555
555
F0
20
Program (14)
Sector Erase (14)
SA
Chip Erase (14)
80
XXX
XXX
2AA
2AA
Reset (15)
90
Chip Erase
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (16)
Erase Resume/Program Resume (17)
Secured Silicon Sector Entry
Secured Silicon Sector Exit (18)
AA
AA
2AA
2AA
55
55
555
555
88
90
XX
00
Legend
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A
–A16 uniquely select any sector.
max
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
Notes
1. See Table 7.1 on page 14 for description of bus operations.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits A
:A16 are don’t cares for unlock and command cycles, unless SA or PA required. (A
is the Highest Address pin.).
MAX
MAX
6. No unlock or command cycles required when reading array data.
November 21, 2006 S29GL-P_00_A3
S29GL-P MirrorBitTM Flash Family
61
SPANSION [ SPANSION ]
