A d v a n c e
I n f o r m a t i o n
Table 22.
Addresses
(x16)
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Addresses
(x8)
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
Data
0027h
0036h
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
System Interface String
Description
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V
PP
Min. voltage (00h = no V
PP
pin present)
V
PP
Max. voltage (00h = no V
PP
pin present)
Reserved for future use
Typical timeout for Min. size buffer write 2
N
µ
s (00h = not supported)
Typical timeout per individual block erase 2
N
ms
Typical timeout for full chip erase 2
N
ms (00h = not supported)
Reserved for future use
Max. timeout for buffer write 2
N
times typical
Max. timeout per individual block erase 2
N
times typical
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Note:
CFI data related to V
CC
and time-outs may differ from actual V
CC
and time-outs of the product. Please consult the Ordering
Information tables to obtain the V
CC
range for particular part numbers. Please consult the Erase and Programming Performance table
for typical timeout specifications.
40
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
SPANSION [ SPANSION ]
