Data
She et
Figure 10.3
Program Suspend/Program Resume
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 20
μs
Read data as
required
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
No
Done
reading?
Yes
Write address/data
XXXh/30h
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
10.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
and
show the
address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.
Refer to
for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a
hardware reset
immediately terminates the erase operation. If this occurs, the chip erase command sequence should be
reinitiated once the device returns to reading array data, to ensure data integrity.
illustrates the algorithm for the erase operation. Refer to
for
parameters, and
for timing diagrams.
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit
®
Flash Family
47
SPANSION [ SPANSION ]
