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S29WS512P0PBFW003 参数 Datasheet PDF下载

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型号: S29WS512P0PBFW003
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内容描述: MirrorBit㈢闪存系列512/256/128 MB( 32/16/8的M× 16位), 1.8 V突发同时读/写的MirrorBit闪存 [MirrorBit㈢ Flash Family 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory]
分类和应用: 闪存
文件页数/大小: 94 页 / 3304 K
品牌: SPANSION [ SPANSION ]
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S29WS-P
MirrorBit
®
Flash Family
S29WS512P, S29WS256P, S29WS128P
512/256/128 Mb (32/16/8 M x 16 bit)
1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
Data Sheet
Features
Single 1.8 V read/program/erase (1.70–1.95 V)
90 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero latency
Random page read access mode of 8 words with 20 ns intra
page access time
32 Word / 64 Byte Write Buffer
Sixteen-bank architecture consisting of
32/16/8 Mwords for 512/256/128P, respectively
Four 16 Kword sectors at both top and bottom of memory
array
510/254/126 64Kword sectors (WS512/256/128P)
Programmable linear (8/16/32) with or without wrap around
and continuous burst read modes
Secured Silicon Sector region consisting of 128 words each
for factory and 128 words for customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of top and bottom sectors
Dual boot sector configuration (top and bottom)
Handshaking by monitoring RDY
Offered Packages
– WS512P/WS256P/WS128P: 84-ball FBGA
(11.6 mm x 8 mm)
Low V
CC
write inhibit
Persistent and Password methods of Advanced Sector
Protection
Write operation status bits indicate program and erase
operation completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming
time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
General Description
The Spansion S29WS512/256/128P are Mirrorbit
®
Flash products fabricated on 90 nm process technology. These burst mode
Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using
separate data and address pins. These products can operate up to 104 MHz and use a single V
CC
of 1.7 V to 1.95 V that
makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power
consumption.
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch Access Time (t
IACC
)
Max. Synch. Burst Access, ns (t
BACC
)
Max OE# Access Time, ns (t
OE
)
Max. Asynch. Access Time, ns (t
ACC
)
104
103.8
7.6
7.6
80
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V
CC
) Per Word
Effective Write Buffer Programming (V
ACC
) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
40 µs
9.4 µs
6 µs
350 ms
600 ms
Current Consumption (typical values)
Continuous Burst Read @ 104 MHz
Simultaneous Operation 104 MHz
Program
Standby Mode
36 mA
40 mA
20 mA
20 µA
Publication Number
S29WS-P_00
Revision
A
Amendment
11
Issue Date
September 28, 2007