A d v a n c e I n f o r m a t i o n
17 Pin Description
Pin Name
CLK
Function
Clock
Type
Description
Commands, Data are referenced to CLK
ADV#
Address Valid
Address valid from ADV# falling edge to ADV# rising edge
MRS# enables Mode Register to be set.
Addresses are loaded as Mode setting is Low
MRS#
Mode Register set
CS# enables the chip to start operating when Low
CS#
Chip Select
CS# disables the chip and puts it into standby mode when High
CS# stops burst operating.during burst operation when High
Input
OE#
WE#
Output Enable
Write Enable
OE# enables the chip to output the data when Low
WE# enables the chip to start writing the data when Low
LB#
UB#
Lower Byte (I/O
)
0~7
UB# (or LB#) enables upper byte (or lower byte) to be
operated when Low
Upper Byte (I/O
)
8~15
Valid addresses input when ADV# is low.
Mode setting inputs during MRS# Low.
A0-A21
Address 0 ~ Address 21
Data Inputs / Outputs
Depending on UB# or LB# status, word (16-bit,
UB#, and LB# low) data, upper byte (8-bit, UB#
low & LB# high) data or lower byte (8-bit, LB# low,
and UB# high) data is loaded
I/O0-I/O15
Input/Output
V
Core Voltage Source
I/O Voltage Source
Core Ground Source
I/O Ground Source
Valid Data Indicator
Do Not Use
Power
Power
GND
Power supply for cells and circuits except for I/O buffer circuits
Power supply for I/O buffer circuits
CC
V
CCQ
V
Ground for cells and circuits except for I/O buffer circuits
Ground for I/O buffer circuits
SS
V
GND
SSQ
WAIT#
DNU
Output
—
WAIT# indicates that output data is invalid when Low
—
102
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
SPANSION [ SPANSION ]
