A d v a n c e I n f o r m a t i o n
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
5
6
7
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data.
Figure 14.10 Linear Burst with RDY Set One Cycle Before Data
14.8.4 AC Characteristics—Asynchronous Read
Parameter
80
MHz
JEDEC Standard
Description
Access Time from CE# Low
54 MHz
66 MHz
Unit
tCE
tACC
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
80
80
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous Access Time
tAVDP
tAAVDS
tAAVDH
tOE
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
7
6
13.5
0
Read
Output Enable Hold Time
Data# Polling
tOEH
10
10
0
tOEZ
tCAS
Output Enable to High Z (see Note)
CE# Setup Time to AVD#
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS128N.
76
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
SPANSION [ SPANSION ]
