Y2210
CY2210
133 MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel
®
CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
• Multiple output clocks at different frequencies
— Four CPU clocks, up to 133 MHz
— Eight synchronous PCI clocks, 1 free-running
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Two reference clocks at 14.318 MHz
Single-chip main motherboard clock generator
— Driven together, support 4 CPUs and a chipset
— Support for 4 PCI slots and chipset
— Drives up to two main memory clock generators, including
DRCG (CPUCLK/2)
— Support for multiple AGP slots
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
Benefits
Usable with Pentium
®
II and Pentium
®
III processors
• Spread Spectrum clocking
Enables reduction of EMI in some systems
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
— 33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
— EPROM programmable percentage of spreading. Default
is –0.6%, which is recommended by Intel
• Power-down features
• Three Select inputs
• Low-skew and low-jitter outputs
• OE and Test Mode support
• 56-pin SSOP package
Supports mobile systems
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
Widely available, standard package enables lower cost
Logic Block Diagram
REFCLK [0–1] (14.318 MHz)
Pin Configuration
Top View
V
SSREF
REFCLK0
REFCLK1
V
DDREF
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
V
DDAPIC
APICCLK2
APICCLK1
APICCLK0
V
SSAPIC
V
DDCPU/2
CPUCLK/2
(DRCG)
CPUCLK/2
(DRCG)
V
SSCPU/2
V
DDCPU
CPUCLK3
CPUCLK2
V
SSCPU
V
DDCPU
CPUCLK1
CPUCLK0
V
SSCPU
AV
DD
AV
SS
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
V
DDUSB
USBCLK
V
SSUSB
CPUCLK [0–3]
CPU_STOP
XTALIN
XTALOUT
14.318
MHz
OSC.
XTALIN
XTALOUT
V
SSPCI
CY2210-2/-3/-4
CPU
PLL
CPUCLK/2 [0–1] (DRCG)
PCICLK_F
PCICLK1
V
DDPCI
SEL1
SEL0
SEL133
SPREAD
PCI_STOP
PWR_DWN
Divider,
EPRO
M-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK_F (33.33 MHz)
PCICLK [1–7] (33.33 MHz)
APICCLK [0–2] (16.67 MHz)
AGPCLK [0–3] (66.67 MHz)
PCICLK2
PCICLK3
V
SSPCI
PCICLK4
PCICLK5
V
DDPCI
PCICLK6
PCICLK7
V
SSPCI
V
SSAGP
AGPCLK0
AGPCLK1
V
DDAGP
V
SSAGP
AGPCLK2
AGPCLK3
V
DDAGP
SEL133
EPROM
SYS
PLL
USBCLK (48 MHz)
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 10
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
