Y2254A
CY2254A
Pentium
®
Processor Compatible Clock Synthesizer/Driver
Features
• Multiple clock outputs to meet requirements of most
Pentium
®
motherboards
— Four pin-selectable CPU clocks @ 66.66 MHz, 60.0
MHz, and 50.0 MHz for support of Intel Triton
™
PCIset
based PC
— 55.0 MHz pin-selectable CPU clock also available ( 2
option only)
— Six PCI clocks at 1/2 CPU Clock frequency
— One I/O clock @ 24 MHz
— One Keyboard Controller clock @ 12 MHz ( 1 option)
or one Universal Serial Bus clock @ 48 MHz
( 2 option)
— Two Ref. clocks @ 14.318 MHz
— Ref. 14.318 MHz Xtal oscillator input
• CPU clock jitter < 200 ps cycle-to-cycle
• Low skew outputs
— < 250 ps between CPU clocks
— < 250 ps between PCI clocks
— < 500 ps between CPU and PCI clocks ( 2 option)
— CPU clock leads PCI clock by +1 ns min. to +4 ns
max. ( 1 option)
• Freq. stability = 0.01% (max.)
• Output duty cycle 45% min. to 55% max.
• Test mode support ( 1 option only)
• 3.3V or 5.0V operation
• Internal pull-up resistors on S0, S1, and OE inputs
Functional Description
The CY2254A is a Clock Synthesizer/Driver that provides the
multiple clocks required for a Pentium-based PC. The
CY2254A has low-skew outputs (< 250 ps between the CPU
Clocks, < 250 ps between the PCI Clocks). In addition, the
CY2254A CPU clock outputs have less than 200 ps
cycle-to-cycle jitter. Finally, both the PCI and CPU clock
outputs meet the 1 V/ns slew rate requirement of a Pentium
processor-based system.
The CY2254A accepts a 14.318 MHz reference signal as its
input. The CY2254A has 2 PLLs, one of which generates the
CPU and PCI clocks, and the other generates the I/O and
Keyboard Controller or USB clocks. The CY2254A runs off
either a 3.3V or 5V supply.
The CY2254A is available in two options. The 1 option
supports the Intel Triton PCIset and provides a 12 MHz
keyboard clock on pin 25. The 2 option provides a 48 MHz
USB clock on pin 25 and supports the Cyrix
®
M1 processor.
Logic Block Diagram
REF0 (14.318 MHz)
REF1 (14.318 MHz)
SYS
PLL
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
ROM
S0
S1
1 option only
2
DELAY
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
OE
2
2
KBDCLK (12 MHz)
IOCLK (24 MHz)
USBCLK (48 MHz)
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
Pin Configuration
Top View
SOIC
V
DD
XTALIN
XTALOUT
V
SS
OE
CPUCLK0
CPUCLK1
V
DD
CPUCLK2
CPUCLK3
V
SS
S1
S0
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REF0
REF1
V
DD
SEEBELOW
IOCLK
V
SS
PCICLK2
PCICLK3
V
DD
PCICLK4
PCICLK5
V
SS
PCICLK1
PCICLK0
OPTION
1
2
PIN 25
KBDCLK
12 MHz
USBCLK
48 MHz
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 7
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