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CY2277APAC-12M 参数 Datasheet PDF下载

CY2277APAC-12M图片预览
型号: CY2277APAC-12M
PDF下载: 下载PDF文件 查看货源
内容描述: Pentium㈢ / II , 6X86 , K6时钟合成器/驱动器,用于桌面/移动PC与Intel㈢ 82430TX和2个DIMM或3 SO- DIMM内存模块 [Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs]
分类和应用: 驱动器PC时钟
文件页数/大小: 18 页 / 293 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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Y2277A
CY2277A
Pentium
®
/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel
®
82430TX and 2 DIMMs or 3 SO-DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of
Pentium
®
, Pentium
®
II, 6x86, or K6 motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
— Seven 3.3V synchronous PCI clocks, one free
running
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
• Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
packages.
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate
enable optimal configurations for EMI control.
.
IOAPIC (14.318 MHz)
V
DDQ2
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
STOP
LOGIC
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium,
Pentium II, 6X86, and K6 portable PCs designed with the Intel
®
Logic Block Diagram
Pin Configuration
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1
REF0
V
SS
XTALIN
XTALOUT
MODE
V
DDQ3
PCICLK_F
PCICLK0
V
SS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
V
DDQ3
PCICLK5
V
SS
SEL
SDATA
SCLK
V
DDQ3
USBCLK/IOCLK
USBCLK/IOCLK
V
SS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AV
DD
PWR_SEL
V
DDQ2
IOAPIC
PWR_DWN
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM4
SDRAM5
V
DDQ3
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AV
DD
CPUCLK[0–3]
V
DDCPU
SEL
MODE
EPROM
SDRAM[0–5]
SDRAM6/CPU_STOP
SYS
PLL
SDRAM7/PCI_STOP
/2
Delay
STOP
LOGIC
SERIAL
INTERFACE
CONTROL
LOGIC
Divide and
Mux Logic
PWR_DWN
SCLK
SDATA
PCI[0–5]
PCICLK_F
USBCLK/IOCLK[0:1]
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
CY2277A-1,-1M,-3,-7M,-12,-12M,-12I
REF [0–1]
(14.318)
Page 1 of 18
www.SpectraLinear.com