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CY2280PVC-11S 参数 Datasheet PDF下载

CY2280PVC-11S图片预览
型号: CY2280PVC-11S
PDF下载: 下载PDF文件 查看货源
内容描述: 100 MHz的Pentium㈢ II时钟合成器/驱动器,具有扩频移动或台式电脑 [100 MHz Pentium㈢ II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs]
分类和应用: 晶体驱动器外围集成电路光电二极管电脑PC时钟
文件页数/大小: 11 页 / 170 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2280
Function Table (-11S Option)
SEL100 SEL1 SEL0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
SEL_SS
[2]
N/A
N/A
N/A
0 (downspread)
1 (no spread)
N/A
N/A
N/A
0 (downspread)
1 (no spread)
CPU/PCI
Ratio
2
2
2
2
2
3
3
3
3
3
CPUCLK
Hi-Z
Reserved
Reserved
PCICLK_F
PCICLK
Hi-Z
Reserved
Reserved
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
[3]
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
[3]
APIC
USBCLK
Hi-Z
48 MHz
48 MHz
48 MHz
48 MHz
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
66.66 MHz 33.33 MHz
66.66 MHz 33.33 MHz
TCLK/2
Reserved
Reserved
100 MHz
100 MHz
TCLK/6
Reserved
Reserved
33.33 MHz
33.33 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Function Table (-21S Option)
SEL100 SEL1 SEL0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
SEL_SS
[2]
N/A
N/A
N/A
0 (downspread)
1 (no spread)
N/A
N/A
N/A
0 (downspread)
1 (no spread)
CPU/PCI
Ratio
2
2
2
2
2
3
3
3
3
3
CPUCLK
Hi-Z
Reserved
Reserved
PCICLK_F
PCICLK
Hi-Z
Reserved
Reserved
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
[3]
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF
Hi-Z
Reserved
Reserved
16.67 MHz
16.67 MHz
TCLK/12
[3]
Reserved
Reserved
16.67 MHz
16.67 MHz
APIC
USBCLK
Hi-Z
48 MHz
48 MHz
48 MHz
48 MHz
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
66.66 MHz 33.33 MHz
66.66 MHz 33.33 MHz
TCLK/2
Reserved
Reserved
100 MHz
100 MHz
TCLK/6
Reserved
Reserved
33.33 MHz
33.33 MHz
Actual Clock Frequency Values
Clock Output
CPUCLK
CPUCLK
USBCLK
Target Frequency Actual Frequency
(MHz)
(MHz)
66.67
100
48.0
66.654
99.77
48.008
PPM
–195
–2346
167
Power Management Logic
CPU_STOP
X
0
0
1
1
PCI_STOP
X
0
1
0
1
0
1
1
1
1
PWR_DWN
CPUCLK
Low
Low
Low
Running
Running
PCICLK
Low
Low
Running
Low
Running
PCICLK_F
Low
Running
Running
Running
Running
Other
Clocks
Low
Running
Running
Running
Running
Osc.
Off
PLLs
Off
Running Running
Running Running
Running Running
Running Running
Notes:
2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.
3. TCLK supplied on the XTALIN pin in Test Mode.
Rev 1.0, November 25, 2006
Page 3 of 11