CY28159
Clock Generator for Serverworks Grand Champion Chipset
Applications
1CY28159
Features
• Eight differential CPU clock outputs
• One PCI output
• One 14.31818 MHz reference clock
• Two 48 MHz clocks
Table 1. Frequency Selection
SEL 100/133
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
S1
0
1
0
1
0
1
0
1
CPU(0:7), CPU#(0:7)
100 MHz
100 MHz
100 MHz
Hi-Z
133.3MHz
133.3MHz
200MHz
N/A
3V33
33.3MHz
33.3MHz
Disable
Hi-Z
33.3MHz
33.3MHz
33.3MHz
N/A
48M(0,1)
48 MHz
Disable
Disable
Hi-Z
48 MHz
Disable
48 MHz
N/A
Notes
Normal Operation
Test Mode(recommended)
Test Mode (optional)
Hi-Z all outputs
Optional
Optional
o7ptional
Reserved
• All outputs compliant with Intel
®
specifications
• External resistor for current reference
• Selection logic for differential swing control, test mode,
Hi-Z, power-down and spread spectrum
• 48-pin SSOP and TSSOP packages
Table 2.
Block Diagram
Pin Configuration
3V33
VDD
48M0/S0
48M1/S1
VSS
VDD
CPU0
CPU0#
VSS
CPU1
CPU1#
VDD
CPU2
CPU2#
VSS
CPU3
CPU3#
VDD
REF
SSCG#
VSS
XIN
XOUT
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
VSS
VDDA
VSSA
PD#
VDD
CPU4
CPU4#
VSS
CPU5
CPU5#
VDD
CPU6
CPU6#
VSS
CPU7
CPU7#
VDD
MULT0
MULT1
VSS
VSSA
IREF
VDDA
XIN
XOUT
MultSel(0:1)
I_Ref
OSC
VDDI
I
Control
REF
CPU (0:7)
CPU (0:7)#
SSCG#
SEL100/133
VCO
48M(0,1)/S(0,1)
PD#
S(0,1)
VDDL
3V33
VSSL
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
CY28159
VSSI
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