CY28325-3
FTG for VIA™ Pentium 4™ Chipsets
Features
•
Spread Spectrum Frequency Timing Generator for VIA
PT/M 266-800 Pentium 4 Chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Selectable hardware or software-programmed clock
frequency when Watchdog Timer time-out
• Capable to generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus Byte Read/Write and Block Read/Write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable-drive strength support
• Programmable-output skew support
• Three copies AGP Clocks
• Power management control inputs
• Available in 48-pin SSOP
CPU
x3
AGP
x3
PCI
x9
REF
x1
APIC
x2
48M
x1
24_48M
x1
Block Diagram
X1
X2
Pin Configuration
VDD_REF
REF
[1]
XTAL
OSC
PLL 1
SSOP-48
*FS4/REF
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS3/48MHz
*FS2/24_48MHz
GND_48MHz
*FS0/PCI_F
*FS1/PCI1
*MULT_SEL1/PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*PD#
AGP0
VDD_AGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_APIC
GND_APIC
APIC0
APIC1
GND_CPU
VDD_CPU_CS(2.5V)
CPUT_CS_F
CPUC_CS_F
CPUT_0
CPUC_0
VDD_CPU(3.3V)
IREF
GND_CPU
CPUT_1
CPUC_1
VTT_PWRGD#
CPU_STOP#*
PCI_STOP#*
RST#
SDATA
SCLK
AGP2
AGP1
GND_AGP
PLL Ref Freq
Divider
Network
Stop
Clock
Control
VDD_CPU_CS (2.5V)
CPUT_CS, CPUC_CS
VDD_CPU (3.3V)
CPUT_0,1, CPUC_0,1
*(FS0:4)
VTT_PWRGD#
*CPU_STOP#
*MULTSEL1
~
VDD_APIC
APIC0:1
VDD_AGP
AGP0:2
CY28325-3
VDD_PCI
PCI_F
PD#
Stop
Clock
Control
PCI1:8
*PCI_STOP#
PLL2
VDD_48MHz
48MHz
24_48MHz
2
SDATA
SCLK
SMBus
Logic
RST#
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
