CY28325-3
Pin Definitions
(continued)
Pin Name
VTT_PWRGD#
No.
33
Type
I
Description
Power-good from Voltage Regulator Module (VRM):
3.3V LVTTL input.
VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4
and MULTSEL inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
2.5V Power Connection:
Power supply for CPU_CS outputs buffers and
APIC output buffers. Connect to 2.5V.
3.3V Power Connection:
Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and 48-MHz
output buffers. Connect to 3.3V.
VDD_CPU_CS,
VDD_APIC
VDD_REF,
VDD_48MHz,
VDD _PCI,
VDD_AGP,
VDD_CPU
GND_REF
GND_48MHz,
GND_PCI,
GND_AGP,
GND_CPU,
GND_APIC
43, 48
2, 6, 16, 24, 38
P
P
3, 9, 13, 20, 25,
36, 44, 47
G
Ground Connection:
Connect all ground pins to the common system
ground plane.
Table 1. Frequency Selection Table
Input Conditions
FS4
SEL4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
FS3
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
FS2
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
FS1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
102.0
105.0
108.0
111.0
114.0
117.0
120.0
123.0
126.0
130.0
136.0
140.0
144.0
148.0
152.0
156.0
160.0
164.0
166.6
170.0
175.0
180.0
AGP
68.0
70.0
72.0
74.0
76.0
78.0
80.0
82.0
63.0
65.0
68.0
70.0
72.0
74.0
76.0
78.0
80.0
82.0
66.6
68.0
70.0
72.0
PCI
34.0
35.0
36.0
37.0
38.0
39.0
40.0
41.0
31.5
32.5
34.0
35.0
36.0
37.0
38.0
39.0
40.0
41.0
33.3
34.0
35.0
36.0
APIC
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
18.0
18.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
16.7
17.0
17.5
18.0
Output Frequency
PLL Gear
Constants
(G)
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
Rev 1.0, November 21, 2006
Page 3 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
