CY28326
Byte 1: Control Register
Bit
7
6
5
4
3
@Pup
1
1
0
0
0
Name/Pin Affected
FS3
FS2
FS1
FS0
FS_Override/FS(D:A)
FS_Override
0 = Select operating frequency by FS(D:A) (HW Strapping) input bits,
1 = Select operating frequency by FSEL[3:0](SW Strapping) settings.
CPU[T/C]2
Powerdown/CPUSTP#
drive mode
0 = Driven in powerdown, 1 = Tri-state
CPU[T/C]1
Powerdown/CPUSTP#
drive mode
0 = Driven in powerdown, 1 = Tri-state
CPU[T/C]0
Powerdown/CPUSTP#
drive mode
0 = Driven in powerdown, 1 = Tri-state
Description
SW frequency selection bits [3:0]. See table 2.
2
1
0
0
0
0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Byte 2: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name/Pin Affected
PCIF[2:0]
PCI[6:0]
AGP[2:0]
Test bit
48 MHz, 24/48 MHz
Reserved
REF[1:0]
Test bit
Description
PCIF Clock Output Drive Strength
0 = Low drive strength, 1 = High drive strength
PCI Clock Output Drive Strength
0 = Low drive strength, 1 = High drive strength
AGP Clock Output Drive Strength
0 = Low drive strength, 1 = High drive strength
Don’t change, Default =0
48 MHz Clock Output Drive Strength
0 = Low drive strength, 1 = High drive strength
Reserved
REF Clock Output Drive Strength
0 = Low drive strength, 1 = High drive strength
Don’t change, Default =0
Byte 3: Control Register
Bit
7
6
5
@Pup
0
1
1
Name/Pin Affected
Spread Spectrum Sel
CPU
AGP
PCIF
PCI
Spread Spectrum Selection
‘000’ = –1.25 ~ 0.25%
‘001’ = –1.0%
‘010’ = –0.75%
‘011’ = –0.5% (default)
‘100’ = ± 0.75%
‘101’ = ± 0.5%
‘110’ = ± 0.35%
‘111’ = ± 0.25%
Description
4
3
2
0
0
0
AGP_SKEW1
AGP_SKEW0
CPU,AGP,PCIF,PCI
AGP Skew control, relative to PCICLK
01 = –300ps
10 = +300ps
11 = +450ps
Spread Spectrum Enable/Disable Function
0 = Spread spectrum disable
1 = Spread spectrum enable
REF1 Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
1
0
1
1
REF1
REF0
Rev 1.0, November 20, 2006
Page 6 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
