CY28346
Pin Description
Pin
2
3
52, 51, 49, 48,
45, 44
10, 11, 12, 13,
16, 17, 18
5, 6, 7
Name
XIN
XOUT
CPUT(0:2),
CPUC(0:2)
PCI(0:6)
PCIF (0:2)
PWR
V
DD
V
DD
V
DDP
V
DD
I/O
I
O
O
O
O
Description
Oscillator Buffer Input.
Connect to a crystal or to an external clock.
Oscillator Buffer Output.
Connect to a crystal. Do not connect when an external
clock is applied at X
IN
.
Differential Host Output Clock Pairs.
See
Table 1
for frequency/functionality.
PCI Clock Outputs.
Are synchronous to 66IN or 3V66 clock. See
Table 1.
33MHz PCI Clocks.
2 copies of 66IN or 3V66 clocks that may be free running
(not stopped when PCI_STP# is asserted LOW) or may be stoppable depending
on the programming of SMBus register Byte3,Bits (3:5).
Buffered Output Copy of the Device’s X
IN
Clock.
Current Reference Programming Input for CPU Buffers.
A resistor is
connected between this pin and VSSIREF.
Qualifying Input that Latches S(0:2) and MULT0.
When this input is at a logic
LOW, the S(0:2) and MULT0 are latched.
Fixed 48 MHz USB Clock Outputs.
Fixed 48 MHZ DOT Clock Outputs.
3.3V 66 MHz Fixed-frequency Clock.
3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5.
When Byte
0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a
logic 0, this is a 66M output clock (default).
Power-down Mode Pin.
A logic LOW level causes the device to enter a
power-down state. All internal logic is turned off except for the SMBus logic. All
output buffers are stopped.
Programming Input Selection for CPU Clock Current Multiplier.
56
42
28
39
38
33
35
REF
IREF
VTT_PG#
48MUSB
48MDOT
3V66_0
3V66_1/VCH
V
DD
V
DD
V
DD
V
DD48
V
DD48
V
DD
V
DD
O
I
I
O
O
O
O
25
PD#
V
DD
I
PU
I
PU
I
I
43
55, 54
29
MULT0
S(0,1)
SDATA
I
I
30
40
34
SCLK
S2
PCI_STP#
I
V
DD
V
DD
53
CPU_STP#
V
DD
24
21, 22, 23
1, 8, 14, 19, 32,
37, 46, 50
4, 9, 15, 20, 27,
31, 36, 47
41
66IN/3V66_5
66B(0:2)/
3V66(2:4)
V
DD
V
SS
V
SS
IREF
V
DD
V
DD
Frequency Select Inputs.
See
Table 1.
Serial Data Input.
Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
I
Serial Clock Input.
Conforms to the SMBus specification.
I
Frequency Select Input.
See
Table 1.
This is a Tri-level input which is driven
T
HIGH, LOW or driven to a intermediate level.
I
PCI Clock Disable Input.
When asserted LOW, PCI (0:6) clocks are synchro-
PU nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’
outputs if they are programmed to be PCIF clocks via the device’s SMBus
interface.
I
CPU Clock Disable Input.
When asserted LOW, CPUT (0:2) clocks are
PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchro-
nously disabled in a LOW state.
I/O
Input Connection for 66CLK(0:2) Output Clock Buffers
if S2 = 1, or output
clock for fixed 66-MHz clock if S2 = 0. See
Table 1.
O
3.3V Clock Outputs.
These clocks are buffered copies of the 66IN clock or fixed
at 66 MHz. See
Table 1.
PWR
3.3V Power Supply.
PWR
Common Ground.
PWR
Current Reference Programming Input for CPU Buffers.
A resistor is
connected between this pin and IREF. This pin should also be returned to device
V
SS
.
PWR
Analog Power Input.
Used for phase-locked loops (PLLs) and internal analog
circuits. It is also specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
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DDA
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Rev 1.0, November 24, 2006
SPECTRALINEAR [ SPECTRALINEAR INC ]
