CY28349B
Pin Definitions
(continued)
Pin Name
PWR_DWN#
SCLK
SDATA
RST#
Pin No.
42
26
25
20
Pin
Type
I
I
I/O
Pin Description
Power-down Control:
3.3V LVTTL compatible input that places the device in
power down mode when held low.
SMBus Clock Input:
Clock pin for serial interface.
SMBus Data Input:
Data pin for serial interface.
O
System Reset Output:
Open-drain system reset output.
(open-d
rain)
I
I
Current Reference for CPU Output:
A precision resistor is attached to this pin
which is connected to the internal current reference.
Powergood from Voltage Regulator Module (VRM):
3.3V LVTTL input.
VTT_PWRGD# is a level-sensitive strobe used to determine when FS0:4 and
MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
3.3V Power Connection:
Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.
Connect to 3.3V.
IREF
VTT_PWRGD#
35
19
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
VDD_CORE
GND_CORE
2, 9, 18, 24,
32, 39, 46
P
5, 13, 21, 29,
36, 43, 47
G
Ground Connection:
Connect all ground pins to the common system ground
plane.
34
33
P
G
3.3V Analog Power Connection:
Power supply for core logic, PLL circuitry.
Connect to 3.3V.
Analog Ground Connection:
Ground for core logic, PLL circuitry.
Rev 1.0, November 20, 2006
Page 3 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
