CY28372
SiS 746 AMD Athlon™/AMD Duron™ Clock Synthesizer
Features
•
Supports AMD Athlon /Duron
• 3.3V and 2.5V power supply
• Eight copies of PCI clocks
• One 48-MHz USB clock
• Two copies of ZCLK clocks
• One 48 MHz/24 MHz programmable SIO clock
CPU
x2
ZCLK
x2
REF
x3
PCI
x8
AGP
x2
IOAPIC
x2
48M
x1
24_48M
x1
• One differential CPU clock (opendrain)
CPU
• One singled-ended CPU clock (opendrain)
• SMBus support with readback capabilities
• Spread Spectrum electromagnetic interference (EMI)
reduction
•
48-pin SSOP package
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF0:2
XTAL
OSC
PLL Ref Freq
Divider
Network
VDD_CPU
CPUT1
CPUT0, CPUC0
VDD_Z
ZCLK0:1
PLL 1
**FS0:3
CPU_STP#
VDD_APIC
APIC0:1
VDD_PCI
PCIF0:1
2
PCI0:5
PCI_STP#
Fract.
Aligner
VDD_AGP
AGP0:1
PLL2
PD#
VDD_48
48 MHz
24_48MHz
2
VDD_REF
**FS0/REF0
**FS1/REF1
REF2
GND_REF
XIN
XOUT
GND_Z
ZCLK0
ZCLK1
VDD_Z
*PCI_STP#
VDD_PCI
**FS2/PCIF0
*FS3/PCIF1
PCI0
PCI1
GND_PCI
VDD_PCI
PCI2
PCI3
PCI4
PCI5
GND_PCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_APIC
IOAPIC1
IOAPIC0
GND_APIC
CPU_STP#*
CPUT1
VDD_CPU
GND_CPU
CPUT0
CPUC0
VDD_CPU
GNDA
VDDA
SCLK
SDATA
PD#*
GND_AGP
AGP0
AGP1
VDD_AGP
VDD_48
48MHZ
24_48MHZ
GND_48
~
SDATA
SCLK
I2C
Logic
SSOP-48
* : Internal Pull-up 150k
** : Internal Pull-down 150k
CY28372
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 17
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
