CY28400
PWRDWN#—Deassertion
The power-up latency is less than 1 ms. This is the time from
the deassertion of the PWRDWN# pin or the ramping of the
power supply or the time from valid SRC_IN input clocks until
the time that stable clocks are output from the buffer chip (PLL
locked). If the control register PWRDWN# three-state bit is
programmed to ‘1’, all differential outputs will be driven HIGH
in less than 300 s of PWRDWN# deassertion to a voltage
greater than 200 mV.
Tstable
<1mS
PWRDWN#
DIFT
DIFC
Tdrive_Pwrdwn#
<300uS, >200mV
Figure 2. PWRDWN# Deassertion Diagram
Table 4. Buffer Power-up State Machine
State
0
1
2
[3]
3
[2]
3.3V Buffer power off
After 3.3V supply is detected to rise above 1.8V–2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay
Buffer
waits for a valid clock on the SRC_IN input
and PWRDWN# deassertion
Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation
No Input Clock
Description
S2
S1
Delay
>0.25ms
Wait for Input
Clock &
PWRDWN# De-
assertion
PWRDWN# Asserted
S0
Power Off
S3
Normal
Operation
Figure 3. Buffer Power-up State Diagram
Notes:
2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).
3. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks
are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled.
Rev 1.0, November 21, 2006
Page 6 of 12
SPECTRALINEAR [ SPECTRALINEAR INC ]
