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CY28401OXCT 参数 Datasheet PDF下载

CY28401OXCT图片预览
型号: CY28401OXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 100 MHz差分缓冲器,用于PCI Express和SATA [100 MHz Differential Buffer for PCI Express and SATA]
分类和应用: 逻辑集成电路光电二极管驱动PC
文件页数/大小: 13 页 / 181 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28401
100 MHz Differential Buffer for PCI Express and SATA
Features
• CK409 or CK410 companion buffer
• Eight differential 0.7V clock pairs
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STOP# power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable
• 48-pin SSOP package
Functional Description
The CY28401 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
SRC_DIV2#
VDD
VSS
SRCT_IN
SRCC_IN
OE_0
OE_3
DIFT0
DIFCO
VSS
VDD
DIFT1
DIFC1
OE_1
OE_2
DIFT2
DIFC2
VSS
VDD
DIFT3
DIFC3
PLL/BYPASS#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_A
VSS_A
IREF
LOCK
OE_7
OE_4
DIFT7
DIFC7
VSS
VDD
DIFT6
DIFC6
OE_6
OE_5
DIFT5
DIFC5
VSS
VDD
DIFT4
DIFC4
HIGH_BW#
SRC_STOP#
PWRDWN#
VSS
DIFT0
OE_[0:7]
SRC_STOP#
PWRDWN#
DIFC0
Output
Control
DIFT1
DIFC1
DIFT2
SCLK
SDATA
SRC_DIV2#
PLL/BYPASS#
SMBus
Controller
Output
Buffer
DIFC2
DIFT3
DIFC3
DIFT4
DIFC4
DIFT5
DIFC5
CY28401
SRCT_IN
SRCC_IN
DIV
HIGH_BW#
DIFT6
DIFC6
PLL
DIFT7
DIFC7
LOCK
48 SSOP
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 13
www.SpectraLinear.com