CY28405-2
Clock Synthesizer with Differential SRC and CPU Outputs
Features
• Supports Intel Pentium
®
4-type CPUs
• Selectable CPU frequencies
• 3.3V power supply
• Nine copies of PCI clocks
• Four copies of 3V66 with one optional VCH
• Two copies 48-MHz clock
CPU
x3
SRC
x1
3V66
x4
PCI
x9
REF
x2
48M
x2
• Three differential CPU clock pairs
• One differential SRC clock
• Support SMBus/I
2
C Byte, Word and Block Read/ Write
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
•
48-pin SSOP package
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF(0:1)
[1]
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
VDD_CPU
CPUT(0:1, ITP), CPUC(0:1, ITP)
VDD_SRCT
SRCT, SRCC
FS_(A:B)
VTT_PWRGD#
IREF
VDD_3V66
3V66_(0:2)
PLL2
2
VDD_PCI
PCIF(0:2)
PCI(0:5)
3V66_3/VCH
VDD_48MHz
DOT_48
USB_48
PD#
SDATA
SCLK
I
2
C
Logic
*FS_A/REF_0
*FS_B/REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PD#
DOT_48
USB_48
VSS_48
VDD_48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
IREF
CPUT_ITP
CPUC_ITP
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
SDATA*
SCLK*
3V66_0
3V66_1
VSS_3V66
VDD_3V66
3V66_2
3V66_3/VCH
~
SSOP-48
* 100k Internal Pull-up
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
CY28405-2
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 16
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
