CY28405
CK409-Compliant Clock Synthesizer
Features
• Supports Intel Springdale/Prescott (CK409)
• Selectable CPU frequencies
• 3.3V power supply
• Nine copies of PCI clock
• Four copies 3V66 clock with one optional VCH
• Two copies 48 MHz USB clock
• Two copies REF clock
CPU
x3
3V66
x4
PCI
x9
REF
x2
48M
x2
• Three differential CPU clock pairs
• Dial-A-Frequency
®
• Supports SMBus/I
2
C Byte, Word, and Block Read/Write
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 48-pin SSOP package
Block Diagram
Pin Configuration
**FS_A/REF_0
**FS_B/REF_1
VDD_REF
VDD_REF
REF[0:1]
XIN
XOUT
VDD_CPU
VSS_REF
CPUT[0:1,ITP], CPUC[0:1,ITP]
*FS_C/PCIF0
*FS_D/PCIF1
*FS_E/PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
VDD_3V66
3V66_[0:2]
PCI2
PCI3
VDD_PCI
VDD_PCI
PCIF[0:2]
VSS_PCI
PCI[0:5]
PCI4
PCI5
RESET#/PD#
DOT_48
3V66_3/VCH
USB_48
VSS_48
VDD_48MHz
VDD_48
DOT_48
USB_48
XIN
XOUT
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
FS_[A:E]
VTT_PWRGD#
IREF
SELVCH
PLL2
2
MODE
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
IREF
CPUT_ITP
CPUC_ITP
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS
DNC***
DNC***
VDD
VTT_PWRGD#
SDATA
SCLK
3V66_0
3V66_1
VSS_3V66
VDD_3V66
3V66_2/MODE*
3V66_3/VCH/SELVCH**
~
SSOP-48
* 150k Internal Pull-up
** 150k Internal Pull-down
*** Do Not Connect
CY28405
SDATA
SCLK
I
2
C
Logic
WD
Timer
RESET#
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
