CY28411
Clock Generator for Intel Alviso Chipset
Features
• Compliant to Intel CK410M
• Supports Intel Pentium-M CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
CPU
x2 / x3
SRC
x7 / x8
PCI
x6
REF
x1
DOT96
x1
USB_48
x1
• 33 MHz PCI clock
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
Block Diagram
XIN
XOUT
CPU_STP#
PCI_STP#
FS_[C:A]
VTT_PWRGD#
IREF
Pin Configuration
VDD_PCI
VSS_PCI
PCI3
VDD_CPU
PCI4
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
PCI5
VDD_SRC
VSS_PCI
SRCT[0:6], SRCC[0:6]
VDD_PCI
PCIF0/ITP_EN
PCIF1
VTT_PWRGD#/PD
VDD_PCI
VDD_48
PCI[2:5]
USB_48/FS_A
VDD_PCIF
VSS_48
PCIF[0:1]
DOT96T
DOT96C
VDD_48 MHz
FS_B/TEST_MODE
DOT96T
SRCT0
DOT96C
SRCC0
USB_48
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRC4_SATAT
SRC4_SATAC
VDD_SRC
VDD_REF
REF
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
PD
PLL2
SDATA
SCLK
I
2
C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2
PCI_STP#
CPU_STP#
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
56 SSOP/TSSOP
CY28411
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
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