CY28437
Byte 14: Control Register 14
Bit
7
@Pup
Name
SRC_N8
Description
0
0
SRC Dial-A-Frequency Bit N8
Software Reset.
6
SW_RESET
When set the device will assert a reset signal on SRESET# upon
completion of the block/word/byte write that set it. After asserting and
deasserting the SRESET# this bit will self clear (set to 0).
The SRESET# pin must be enabled by latching SRESET#_EN on
VTT_PRWGD# to utilize this feature.
5
4
0
0
FS_[E:A]
FS_Override
0 = Select operating frequency by FS(D:A) input pins
1 = Select operating frequency by FSEL_(3:0) settings
SMSW_SEL
Smooth switch select
0: Select CPU_PLL
1: Select SRC_PLL
3
2
1
0
0
1
RESERVED
RESERVED
PCIF
RESERVED, Set = 0
RESERVED, Set = 0
Free running 33-MHz Output Drive Strength
0 = 2x, 1 = 1x
0
0
Recovery_N8
Watchdog Recovery Bit
Byte 15: Control Register 15
Bit
7
@Pup
Name
Description
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
0
0
0
0
0
0
0
0
Recovery N7
Recovery N6
Recovery N5
Recovery N4
Recovery N3
Recovery N2
Recovery N1
Recovery N0
6
5
4
3
2
1
0
Byte 16: Control Register 16
Bit
@Pup
Name
Description
7
1
REF1
REF1 Output Enable
0 = Disable, 1 = Enable
6
5
1
0
USB48_1
USB48_1 Output Enable
0 = Disable, 1 = Enable
SRC_FREQ_SEL
SRC Frequency selection
0: SRC frequency is selected via the FSE pin
1: SRC frequency is initially set to 167 MHz.
4
3
0
0
RESERVED
SRC_SATA
RESERVED, Set = 0
SATA PLL Spread Spectrum Enable
0 = Spread off, 1 = Spread on
2
1
0
0
0
1
Prog_SRC_EN
Prog_CPU_EN
Programmable SRC frequency enable
0 = Disabled, 1 = Enabled.
Programmable CPU frequency enable
0 = Disabled, 1 = Enabled.
Watchdog Autorecovery Watchdog Autorecovery Mode
0 = Disable (Manual), 1= Enable (Auto)
Rev 1.0,November 20, 2006
Page 10 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
