CY28437
Byte 8: Control Register 8
Bit
7
@Pup
0
Name
CPU_SS
Description
Spread Selection for CPU PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
Spread Selection for CPU PLL
0: Down spread
1: Center spread
SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Spread Selection for SRC PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
RESERVED, Set = 0
48-MHz Output Drive Strength
0 = 2x, 1 = 1x
33-MHz Output Drive Strength
0 = 2x, 1 = 1x
RESERVED, Set = 0
6
0
CPU_DWN_SS
5
4
0
0
SRC_SS_OFF
SRC_SS
3
2
1
0
0
1
1
0
RESERVED
USB
PCI
RESERVED
Byte 9: Control Register 9
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
DF_Limit2
DF_Limit1
DF_Limit0
DF_EN
FSEL_D
FSEL_C
FSEL_B
FSEL_A
Dynamic Frequency Enable
0 = Disable, 1 = Enable
SW Frequency selection bits. See
Table 1.
Description
Dynamic Frequency Max threshold. These three bits will set the max
allowed CPU frequency for Dynamic Frequency
Byte 10: Control Register 10
Bit
7
@Pup
0
Name
Recovery_Frequency
Description
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use HW settings, 1: Recovery N[8:0]
Timer_SEL selects the WD reset function at SRESET pin when WD time
out.
0 = Reset and Reload Recovery_Frequency
1 = Only Reset
Time_Scale allows selection of WD time scale
0 = 294 ms 1 = 2.34 s
WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp.
Watchdog timer time stamp selection
000: Reserved (test mode)
001: 1 * Time_Scale
010: 2 * Time_Scale
011: 3 * Time_Scale
100: 4 * Time_Scale
101: 5 * Time_Scale
110: 6 * Time_Scale
111: 7 * Time_Scale
6
0
Timer_SEL
5
4
3
2
1
1
0
0
0
0
Time_Scale
WD_Alarm
WD_TIMER2
WD_TIMER1
WD_TIMER0
Rev 1.0, November 20, 2006
Page 8 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
