CY28439-2
Clock Generator for Intel Grantsdale Chipset
Features
• Compliant to Intel CK410
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks (two selectable
between Fixed and Overclocking)
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• Dial-A-Frequency
• Watchdog
• Two independent overclocking PLLs
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
•
56-pin SSOP and TSSOP packages
CPU SRC
x2
x6
PCI
x9
REF DOT96
x2
x1
USB
x1
24-48M
x1
Block Diagram
Xin
Xout
Pin Configuration
VDD_RE
F
RE
F
14.318MHz
Crystal
PLL Reference
IREF
VDD_CPU
CPUT
CPUC
PLL1
CPU
FS_[E:A]
Divider
VDD_SRC
SRCT (PCI Ex)
SRCC (PCI Ex)
PLL2
SRC
Divider
VDD_SRC
PLL3
SATA
Divider
SRCT4_SATA
SRCC4_SATA
VDD_48Mhz
PLL4
Fixed
Divider
DOT96T
DOT96C
VDD_48
USB48
VDD_48
24/48
VDD_PCI
PCI
VDD_PCI
PCIF
VTTPWR_GD#/PD
VSS_PCI
PCI3
*FS_E/PCI4
PCI5
VSS_PCI
VDD_PCI
PCIF0
**FS_A/PCIF1
*FS_B/PCIF2
VDD_48
**SEL24_48#/24_48M
USB48
VSS_48
DOT96T
DOT96C
VTTPWRGD#/PD
SRCT0
SRCC0
VDD_SRC
VSS_SRC
SRCT1
SRCC1
SRCT2
SRCC2
VSS_SRC
SRCT_SATAT
SRCC_SATAC
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_PCI
PCI2
PCI1
PCI0
SRESET#
REF1/FS_D**
REF0/FS_C**
VSS_REF
XIN
XOUT
VDD_REF
SCLK
SDATA
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
IREF
VSSA
VDDA
VDD_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VSS_SRC
* Indicates internal pull-up
** Indicates internal pull-down
CY28439-2
SDATA
SCLK
I2C
Logic
Watchdog
Timer
SRESET#
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 21
www.SpectraLinear.com
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