CY28443-3
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
RESERVED
RESERVED
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
RESERVED
SRC[T/C]0
/100M[T/C]_SST
Description
RESERVED
RESERVED
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED, Set = 1
SRC[T/C]0 /100M[T/C]_SST Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Name
PCIF0
27M_nss_DOT_96[T/C]
USB_48MHz
RESERVED
REF1
CPU[T/C]1
CPU[T/C]0
CPU, SRC, PCI, PCIF
spread enable
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
27M nonspread and DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
RESERVED
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
RESERVED
RESERVED
CPU[T/C]2
PCIF1
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
RESERVED
RESERVED
CPU[T/C]2 Output Enable
0 = Disabled (Hi-Z), 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Description
Rev 1.0, November 20, 2006
Page 5 of 23
SPECTRALINEAR [ SPECTRALINEAR INC ]
