CY28510
Peripheral I/O Clock Generator
Features
• 15 33.27 MHz or 66.669-MHz clock outputs
• 1 REF 14.318 MHz
• Divide by 2, spread spectrum and output enable all
selectable on a per-output basis via I
2
C register bits
• Divide by 2 mode default values strappable on a
per-group basis
• Output Enable pin controls all outputs
• I
2
C Compatible Programmability With Block and Byte
Modes
• I
2
C Operates Up to 1MHz
• I
2
C Address Selection of D0, D2, D4 or D6
• 48-Pin SSOP Package
Block Diagram
XIN
REF
Pin Configuration
Mux
Mux
PLL 1with
Spread
Spectrum
Mux
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CLKG0_0
CLKG0_1
CLKG0_2
CLKG0_3
CLKG0_4
CLKG0_5
CLKG0_6
CLKG0_7
CLKG1_0
CLKG1_1
CLKG1_2
CLKG1_3
CLKG2_0
CLKG2_1
CLKG3
66MHz
Mux
Mux
Mux
Mux
(Group Frequency Select, 33 or 66MHz)
Mux
CLK_STOP#
PLL 2 no
Spread
Spectrum
66MHz
GFS0
Mux
SCLK
SDATA
ADDSEL(0:1)
I2C
Mux
Mux
Mux
GFS3
REF
GFS0
VDDX
VSSX
XIN
XOUT
VDDC
ADDSEL0
ADDSEL1
VSSC
CLK_STOP#
SCLK
SDATA
GFS1
GFS2
OE
CLKG3
VDDQ3
VSSQ3
VSSQ2
CLKG2_1
CLKG2_0
VDDQ2
GFS1
Mux
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ0
CLKG0_0
CLKG0_1
VSSQ0
CLKG0_2
VDDQ0
VSSQ0
CLKG0_3
CLKG0_4
VDDQ0
CLKG0_5
CLKG0_6
CLKG0_7
VSSQ0
VDDQ1
CLKG1_0
CLKG1_1
VSSQ1
VDDQ1
CLKG1_2
CLKG1_3
VSSQ1
VDDA
VSSA
CY28510
Mux
GFS2
Mux
GFS3
OE
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 12
www.SpectraLinear.com
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