CY28RS600
Clock Generator for ATI
Features
• Supports Intel CPU
• Selectable CPU frequencies
• Differential CPU clock pairs (30% over/10%under
clocked)
• 100 MHz differential ATI Graphics clocks (100%
over/10% under clocked)
• 100 MHz differential SRC clocks (10% over/under
clocked)
RS5XX, 6XX Chipsets
• 48 MHz USB clock
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 64-pin TSSOP packages
CPU
x3
SRC
x8
ATIG
X4
REF
x3
USB_48
x2
Block Diagram
Pin Configuration
VDD_REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS_REF
FSA_REF0
FSB_REF1
FSC_REF2
RESET_IN#
CPU_STOP#
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
CPUT2
CPUC2
VDDA
VSSA
VSSSRC
SRCT0
SRCC0
VSS_SRC
VDD_SRC
ATIGT0
ATIGC0
ATIGT1
ATIGC1
VDD_ATIG
VSS_ATIG
ATIGT2
ATIGC2
ATIGT3
ATIGC3
CLKREQC#
XIN
XOUT
14.318MHz
Crystal
PLL Reference
VDD
REF[0:2]
VDD_CPU
CPUT[0:2]
CPUC[0:2]
XIN
XOUT
VDD48
USB48_0
USB48_1
VSS48
VTTPWRGD#/PD
CPU
PLL
CLKREQ# [C:A]
RESET_IN#
FS[C:A]
SRC
PLL
Divider
SCLK
SDATA
CLKREQA#
Divider
VSS_SRC
SRCT6
SRCC6
SRCT5
CY28RS600
VDD_ATIG
ATIGT[0:3]
ATIGC[0:3]
SRCT7
SRCC7
VDD_SRC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SRC
PLL
Divider
VDD_SRC
SRCT[0:7]
SRCC[0:7]
SRCC5
SRCT4_SATAT
SRCC4_SATAC
VSS_SRC
VDD_SRC
SRCT3
Fixed
PLL
VTT_PWRGD#/PD
SDATA
SCLK
I2C
Logic
Divider
VDD48
USB48[1:0]
SRCC3
SRCT2
SRCC2
VDD_SRC
VSS_SRC
SRCT1
SRCC1
CLKREQB#
64 TSSOP
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 17
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
