CY2SSTU32866
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant
Data Register with Parity
Features
• Operating frequency: DC to 500 MHz
• Supports DDRII SDRAM
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-10)
• 96-ball FBGA
CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,
the Qn outputs will function normally. The RESET# input has
priority over the DCS# and CSR# control and will force the
outputs LOW. If the DCS#-control functionality is not desired,
the CSR# input can be hardwired to ground, in which case the
set-up time requirement for DCS# would be the same as for
the other D data inputs.
The device supports low-power standby operation. When the
reset input (RESET#) is LOW, the differential input receivers
are disabled, and undriven (floating) data, clock, and reference
voltage (VREF) inputs are allowed. In addition, when RESET#
is LOW, all registers are reset and all outputs are forced LOW.
The LVCMOS RESET# and Cn inputs must always be held at
a valid logic HIGH or LOW level. To ensure defined outputs
from the register before a stable clock has been supplied,
RESET# must be held in the LOW state during power-up.
In the DDR-II RDIMM application, RESET# is specified to be
completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven low quickly, relative to the time to
disable the differential input receivers. However, when coming
out of reset, the register will become active quickly, relative to
the time to enable the differential input receivers.
Functional Description
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to
drive the DDR-II DIMM load. The CY2SSTU32866 operates
from a differential clock (CK and CK#). Data are registered at
the crossing of CK going high, and CK# going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when LOW) to B configuration (when
HIGH). The C1 input controls the pinout configuration from
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device monitors both DCS# and CSR# inputs and will gate
the Qn outputs from changing states when both DCS# and
Pin Configuration
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CK
CK#
D8
D9
D10
D11
D12
D13
D14
1
2
PPO
D15
D16
QERR#
D17
D18
RST#
DCS#
CSR#
D19
D20
D21
D22
D23
D24
D25
2
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
3
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
4
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS#
ZOH
Q8
Q9
Q10
Q11
Q12
Q13
Q14
5
6
NC
Q15
Q16
NC
Q17
Q18
C0
NC
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CK
CK#
D8
D9
D10
D11
D12
D13
D14
1
2
PPO
NC
NC
QERR#
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
3
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
4
5
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
5
6
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
QCSB#
ZOL
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
Q14B
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
D1
D2
D3
D4
D5
D6
PAR_IN
CK
CK#
D8
D9
D10
DODT
D12
D13
DCKE
1
2
PPO
NC
NC
QERR#
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
3
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
4
5
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
5
6
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
QCSB#
ZOL
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
6
1:1 Register C0 = 0, C1=0
1:2 Register A C0 = 0, C1=1
1:2 Register B C0 = 1, C1=1
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 24
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