CY2SSTV8575
Differential Clock Buffer/Driver
Features
• Operating frequency: 60 MHz to 170 MHz
• Supports 266 MHz DDR SDRAM
• 5 differential outputs from 1 differential input
• Spread Spectrum compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power Management Control input
• High-impedance outputs when input clock < 20 MHz
• 2.5V operation
• 32-pin TQFP JEDEC MS-026 C
Description
The CY2SSTV8575 is a high-performance, low-skew, low jitter
zero-delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTV8575 generates five
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTV8575 features differential
feedback clock outputs and inputs. This allows the
CY2SSTV8575 to be used as a zero-delay buffer.
When used as a zero-delay buffer in nested clock trees, the
CY2SSTV8575 locks onto the input reference and translates
with near zero delay to low-skew outputs.
Block Diagram
Pin Configuration
FBOUT#
FBOUT
FBIN#
VSS
OE
VDDQ
FBIN
2
1
OE
AVDD
23
8
32 31 30 29 28 27 26 25
VSS
VDDQ
Y3
Y3#
VDDQ
Y4
Y4#
9 10 11 12 13 14 15 16
AVDD
Test and
Powerdown
Logic
12
11
15
16
27
28
30
31
18
19
Y0
Y0#
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
FBOUT
FBOUT#
24 23 22 21 20 19 18 17
Y2#
Y2
VSS
VDDQ
Y1
Y1#
VSS
AVSS
CY2SSTV8575
TQFP-32
JEDEC MS-026 C
CLK
CLK#
FBIN
FBI
#
N
5
6
21
22
PLL
VSS
1 2 3 4 5 6 7 8
VDDQ
CK
CK#
Y0#
Y0
VDDQ
VDDQ
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
VSS
Page 1 of 7
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
