W256
Figure 1
shows the differential clock directly terminated by a
120 resistor.
V
CC
V
C
C
Device
Under
Test
Out
)
)
60
VTR
R
T
=120
Out
60
VCP
Receiver
Figure 1. Differential Signal Using Direct Termination Resistor
Layout Example Single Voltage
+3.3V Supply or 2.5V Supply
FB
VDD
0.005 F
10 F
C2
G
G
C1
G
G
G
1
G
2
3
4
G
5
V
6
G
7
8
9
V
10
11
G
12
13
14
V
G
28
27
26
V
25
G
24
23
22
V
21
G
20
19
18
G
17
16
15
G
G
W256
@ 100 MHz)
C2 = 0.005 µF
G
FB = Dale ILB1206 – 300 (300
Cermaic Caps C1 = 10–22 µF
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a
ferrite bead and capacitors
All bypass caps = 0.1 F ceramic
Rev 1.0, November 25, 2006
Page 6 of 7