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SL15300 参数 Datasheet PDF下载

SL15300图片预览
型号: SL15300
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程扩频时钟发生器( SSCG ) [Programmable Spread Spectrum Clock Generator (SSCG)]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 368 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL15300
Operating Supply Current
Standby Current
Output Leakage Current
Programmable
Input Capacitance at
Pins 2 and 3
Input Capacitance
IDD
ISBC
IOL
FIN=30MHz and all 4 clocks are
at 66MHz and +/-2.0% Spread
and CL=0
PD#=GND
Pins 4, 6, 7 and 8 if
programmed as SSCLK or
REFOUT
Minimum setting value
Maximum setting value
Resolution (programming steps)
CIN2
CL
Pins 4 and 8 if programmed as
PD#, OE, SSON or FS
Pins 4, 6, 7 and 8 If
programmed as SSCLK or
REFCLK
-
-
-10
-
-
-
-
-
7.9
70
-
7
38
0.5
4
-
9.4
90
10
-
-
-
6
15
mA
μA
μA
pF
pF
pF
pF
pF
PCin
PCout
Load Capacitance
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C
Parameter
Input Frequency Range
Input Frequency Range
Symbol
FIN1
FIN2
Condition
Crystal or Ceramic Resonator
External Clock
SSCLK
REFCLK, crystal or resonator input
REFCLK, clock input
SSCLK
REFCLK , Xtal input
REFCLK, clock input
Clock Input, Pin 3
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Min
8
3
3
0.25
0.25
45
45
40
40
-
-
-
-
-
-
-
Typ
-
-
-
-
-
50
50
50
50
4.00
2.00
1.40
1.10
0.85
0.70
0.55
Max
48
166
200
48
166
55
55
60
60
4.80
2.40
1.70
1.35
1.00
0.85
0.67
Unit
MHz
MHz
MHz
MHz
MHz
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
Output Frequency Range
FOUT1
Output Frequency Range
FOUT2
Output Frequency Range
FOUT3
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Input Duty Cycle
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
DC1
DC2
DC3
DCIN
tr/f1
tr/f2
tr/f3
tr/f4
tr/f5
tr/f6
tr/f7
Rev 1.0, August 14, 2008
Page 5 of 16