SL2304NZ
Switching Electrical Characteristics (I-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Output Fall Time
CLKIN High or Low Time
tf
tHL
CL=25pF, measured at 0.8V to 2.0V
CLKIN=66MHz, CL=15pF
CLKIN=140MHz, CL=15pF
Output to Output Skew
Part to Part Skew
SKW1
SKW2
Measured at VDD/2 and
Outputs are equally loaded
Measured at VDD/2 and
Outputs are equally loaded
Measured at VDD/2 from CLKIN to
Output Clock rising edge and Outputs
are equally loaded
CLKIN=66MHz and CL=0 (No Load)
CLKIN=133MHz and CL=0 (No Load)
–
5
2
–
–
–
–
–
50
90
1.6
–
–
100
200
ns
ns
ns
ps
ps
Propagation Delay Time
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
PDT
CCJ1
CCJ2
–
–
–
3.2
70
50
4.0
140
100
ns
ps
ps
External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1 F must be used between VDD and VSS pins. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and
to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pin.
Series Termination Resistor:
A series termination resistor is recommended if the distance between the output
clocks and the load is over 1 �½ inch. Place the series termination resistors as close to the clock outputs as possible.
Rev 1.3, May 16, 2007
Page 7 of 9
SPECTRALINEAR [ SPECTRALINEAR INC ]
