SL2305
Switching Specifications:
Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
FMAX1
Description
Maximum Frequency
(Input=Output )
All Active PLL Modes
[1]
Condition
High drive (-1H). All outputs CL=15pF
High drive (-1H), All outputs CL=30pF
Standard drive, (-1), All outputs CL=15pf
Standard drive, (-1), All outputs CL=30pf
Min
10
10
10
10
30
40
–
–
–
–
–
–
Max
140
100
100
66
70
60
1.5
1.8
2.2
2.5
120
400
Unit
MHz
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ps
ps
INDC
OUTDC
tr/f
Input Duty Cycle
Output Duty Cycle
[2]
Measured at 1.4V, Fout=66MHz,
CL=15pF
Measured at 14V, Fout=66MHz,
CL=15pF
[2]
Rise, Fall Time (3.3V)
(Measured at: 0.8 to 2.0V)
High drive (-1H), CL=10pF
High drive (-1H), CL=30pF
Standard drive (-1), CL=10pF
Standard drive (-1), CL=30pF
t1
t2
t3
Output-to-Output Skew
(Measured at VDD/2)
[2]
All outputs CL=0 or equally loaded, -1 or
-1H drives
All outputs CL=0 or equally loaded, -1 or
-1H drives
Measured at VDD/2
Device-to-Device Skew
(Measured at VDD/2)
[2]
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
[2]
Edge
PLL Lock Time
[2]
–150
Time from 90% of VDD to valid clocks on
all the output clocks
150
ps
tPLOCK
CCJ
–
–
–
–
–
1.0
90
100
120
140
ms
ps
ps
ps
ps
Cycle-to-cycle Jitter
[2]
Fin=Fout=66 MHz, <CL=15pF, -1H drive
Fin=Fout=66 MHz, <CL=15pF, -1 drive
Fin=Fout=66 MHz, <CL=30pF, -1H drive
Fin=Fout=66 MHz, <CL=30pF, -1 drive
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Rev 1.4, May 25, 2007
Page 6 of 11
SPECTRALINEAR [ SPECTRALINEAR INC ]
