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SL23EP04SC-2HT 参数 Datasheet PDF下载

SL23EP04SC-2HT图片预览
型号: SL23EP04SC-2HT
PDF下载: 下载PDF文件 查看货源
内容描述: 低抖动和偏斜10到220兆赫零延迟缓冲器( ZDB ) [Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer(ZDB)]
分类和应用:
文件页数/大小: 14 页 / 164 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL23EP04
Switching Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Output Rise/Fall Time
Output-to-Output Skew
on Same Bank
Output-to-Output Skew
on Same Bank
Output-to-Output Skew
Between Bank A and B
Output-to-Output Skew
Between Bank A and B
Device-to-Device Skew
tr/f4
SKW1
SKW2
SKW3
SKW4
SKW5
CL=15pF -1H and -2H version
-1 and -2 measured at VDD/2
and outputs are equally loaded
-1H and -2H measured at VDD/2
and outputs are equally loaded
-1 and -2 measured at VDD/2
and outputs are equally loaded
-1H and -2H measured at VDD/2
and outputs are equally loaded
All versions, measured at VDD/2 and
outputs are equally loaded
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Fout=66.6 MHz and CL=15pF
Cycle-to-Cycle Jitter
(-1 and, -2 Versions)
CCJ1
Fout=66.6MHz and CL=30PF
Fout=133.3MHz and CL=15pF
Fout=66.6 MHz and CL=15pF
Cycle-to-Cycle Jitter
(-1H and -2H Versions)
CCJ2
Fout=66.6MHz and CL=30PF
Fout=166.6MHz and CL=15pF
PLL Lock Time
tLOCK
From 0.95VDD and valid clock
presented at CLKIN
-
-
-
-
-
-
-
70
60
110
90
150
1.2
150
125
250
200
400
ns
ps
ps
ps
ps
ps
Input-to-Output Delay
Dt
-200
-
-
-
-
-
-
-
+/-70
50
70
40
40
60
35
-
200
100
150
80
80
130
70
1.0
ps
ps
ps
ps
ps
ps
ps
ms
Operating Conditions (I-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Operating Voltage
Operating Temperature
Input Capacitance
Symbol
VDD
TA
VIH
Condition
VDD+/-10%
Ambient Temperature
Pins 1 and 8
Min
2.97
-40
-
Typ
3.3
-
5
Max
3.63
85
8
Unit
V
°C
pF
Rev 1.1, May 25, 2007
Page 6 of 14