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SL23EP09SC-1H 参数 Datasheet PDF下载

SL23EP09SC-1H图片预览
型号: SL23EP09SC-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低抖动和偏斜10到220MHz的零延迟缓冲器( ZDB ) [Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)]
分类和应用:
文件页数/大小: 13 页 / 157 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL23EP09
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 220 MHz operating frequency range
Low output clock skew: 45ps-typ
Low output clock jitter:
25 ps-typ cycle-to-cycle jitter
15 ps-typ period jitter
Low part-to-part output skew: 90 ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
26 mA-max at 66 MHz and VDD=3.3 V
24 mA-max at 66 MHz and VDD=2.5V
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Description
The SL23EP09 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP09 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs are
needed, four (4) bank-B output clock buffers can be tri-stated
to reduce power dissipation and jitter. The select inputs can
also be used to tri-state both banks A and B or drive them
directly from the input bypassing the PLL and making the
product behave like a Non-Zero Delay Buffer (NZDB).
The high-drive version operates up to 220MHz and 200MHz
at 3.3V and 2.5V power supplies respectively.
Applications
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embeded Systems
Benefits
Up to nine (9) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Pow er and
Low Jitter
P LL
C LKIN
MUX
CLK OU T
CLK A1
CLK A2
C LKA3
CLKA4
S2
Input Selection
Decoding Logic
S1
CLKB1
C LKB2
C LKB3
2
2
C LKB4
VD D
GN D
Rev 1.1, February 2, 2007
Page 1 of 13
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com