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SL38000ZC-XXXT 参数 Datasheet PDF下载

SL38000ZC-XXXT图片预览
型号: SL38000ZC-XXXT
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程4 -PLL CG与VCXO和SSCG [Programmable 4-PLL CG with VCXO and SSCG]
分类和应用: 石英晶振压控振荡器
文件页数/大小: 12 页 / 368 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL38000  
VIN=VDD, Input Pins are  
programmed as PD#, OE, SSON#  
or FS, and no pull-up/down resister  
used  
Input High Current  
Input Low Current  
IIH  
IIL  
-10  
-10  
-
-
10  
10  
μA  
μA  
VIN=GND, Input Pins are  
programmed as PD#, OE, SSON#  
or FS, and no pull-up/down resister  
used  
Pull-up or Down  
Resistors  
If Programmed at pins PD#, OE,  
SSON#, FS and CLKOUT  
RPU/D  
IDD1  
100  
-
175  
16  
250  
kΩ  
FIN=27MHz and all 7 clocks are  
at 33MHz and CL=0  
Operating Supply  
Current  
TBD  
mA  
FIN=27MHz and all 9 clocks are  
at 66MHz and CL=0  
Operating Supply  
Current  
IDD2  
-
22  
TBD  
mA  
Standby Current  
ISBC  
IOL  
PD#=GND  
-
90  
-
120  
μA  
μA  
pF  
pF  
pF  
Output Leakage Current  
OE=GND at CLKOUT pins  
Minimum setting value  
Maximum setting value  
Resolution (programming steps)  
-10  
10  
-
-
-
-
8
Programmable  
Cin  
Input Capacitance at  
Pins 1 and 28  
40  
0.5  
-
Cout  
-
Pins 4 and 8 if programmed as  
PD#, OE, SSON or FS  
Input Capacitance  
Load Capacitance  
CIN2  
CL  
-
-
4
-
6
pF  
pF  
All CLKOUT outputs  
15  
AC Electrical Characteristics (C-Grade)  
Unless otherwise stated VDDA=VDDX= 2.5V to 3.3V+/-10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C  
Parameter  
Symbol  
FIN1  
Condition  
Crystal or Ceramic Resonator  
External Clock  
Min  
8
Typ  
Max  
48  
Unit  
MHz  
MHz  
MHz  
MHz  
MHz  
%
Input Frequency Range  
Input Frequency Range  
Output Frequency Range  
Output Frequency Range  
Output Frequency Range  
Output Duty Cycle  
-
-
FIN2  
3
166  
200  
166  
48  
FOUT1 CLKOUT, VDDO=3.3V to 2.5V  
FOUT2 CLKOUT, VDDO=1.8V  
3
-
3
-
FOUT3 REFCLK, crystal or resonator input  
0.25  
45  
45  
40  
40  
-
-
DC1  
DC2  
SSCLK  
50  
50  
50  
50  
180  
55  
Output Duty Cycle  
REFCLK , Xtal input  
REFCLK, clock input  
Clock Input, Pin 3  
55  
%
Output Duty Cycle  
DC3  
60  
%
Input Duty Cycle  
DCIN  
CCJ1  
60  
%
Cycle-to-Cycle Jitter  
FIN=27MHz, all 7 clocks are  
TBD  
ps  
programmed at 66MHz, CL=15pF  
(SSCLK – Pins 4/6/7/8)  
Cycle-to-Cycle Jitter  
CCJ2  
tPSR  
FIN=27MHz, all 9 clocks are  
programmed at 66MHz, CL=15pF  
-
-
220  
-
TBD  
12  
ps  
(SSCLK – Pins 4/6/7/8)  
Time for VDD reaching minimum  
specified value and monolitic power  
supply ramp  
ms  
Power supply Ramp  
Time  
Rev 1.1, August 7, 2008  
Page 5 of 12