W158
W158
Spread Spectrum System Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel® CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• Eight copies of PCI output (synchronous w/CPU output)
• Four copies of 66 MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
• Three copies of 16.67 MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48 MHz USB output
• Two copies of 14.31818 MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and
shut down
• Available in 56-pin SSOP
...............................................................................................
V
DDQ2
= 2.5V±5%
CPU Output Jitter: ...................................................... 150 ps
CPUdiv2, IOAPIC Output Jitter: .................................. 250 ps
48 MHz, 3V66, PCI Output Jitter: ................................ 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: ....................................... 500 ps
3V66_0:3, IOAPIC0:2 Output Skew: ........................... 250 ps
CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset:............. 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-k
resistors
Table 1. Pin Selectable Frequency
[1]
SEL133/100#
1
0
CPU0:3 (MHz)
133 MHz
100 MHz
PCI
33.3 MHz
33.3 MHz
pull-up
Key Specifications
Supply Voltages: ...................................... V
DDQ3
= 3.3V±5%
Note:
1. See
Table 2
for complete mode selection details.
Block Diagram
X1
X2
CPU_STOP#
Pin Configuration
2
REF0:1
XTAL
OSC
STOP
Clock
Logic
4
CPU0:3
2
SPREAD#
SEL0
SEL1
SEL133/100#
÷2/÷1.5
÷2
CPUdiv2_0:1
PLL 1
STOP
Clock
Logic
4
3V66_0:3
1
PCI_F
STOP
Clock
Logic
7
PCI1:7
PWRDWN#
PCI_STOP#
÷2
Power
Down
Logic
3
÷2
IOAPIC0:2
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
IOAPIC2
IOAPIC1
IOAPIC0
GND
VDDQ2
CPUdiv2_1
CPUdiv2_0
GND
VDDQ2
CPU3
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDDQ3
48MHz
GND
W158
Three-state
Logic
PLL2
1
48MHz
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 12
www.SpectraLinear.com
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