W191
Skew Controlled SDRAM Buffer
Features
• Six skew controlled CMOS outputs
• Output skew between any two outputs is less than 150 ps
• SMBus Serial configuration interface
• 2.5 ns to 5 ns propagation delay
• DC to 133 MHz operation (Commercial)
• DC to 100 MHz operation (Industrial)
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 16-pin SSOP
(Small Shrink Outline Package)
Key Specifications
Supply Voltages: ...................................... V
DDQ3
= 3.3V ±5%
Operating Temperature: (Commercial) ............. 0°C to +70°C
Operating Temperature: (Industrial) .............. –40°C to +85°C
Input Threshold:...................................................1.5V typical
Maximum Input Voltage: .................................. V
DDQ3
+ 0.5V
Input Frequency: (Commercial) ........................0 to 133 MHz
Input Frequency: (Industrial).............................0 to 100 MHz
BUF_IN to SDRAM0:5 Propagation Delay:.......2.5 ns to 5 ns
Min. Output Edge Rate: ............................................. 1.0V/ns
Max. Output Skew: ..................................................... 150 ps
Output Duty Cycle:...................................45/55% worst case
Output Impedance: ...................................................15 typ.
Block Diagram
Pin Configuration
[1]
SDRAM0
GND
SDRAM0
SDRAM1
SDRAM2
SDATA
SCLOCK
SMBus
Device Control
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDQ3
SDRAM5
GND
SDRAM4
VDDQ3
SDRAM3
GND
SCLK
SDRAM1
BUF_IN
GND
SDRAM2
VDDQ3
SDATA
BUF_IN
SDRAM3
SDRAM4
SDRAM5
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLK.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 9
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