W305B
Pin Definitions
Pin Name
REF2X/FS3
Pin No.
3
Pin
Type
I/O
Pin Description
Reference Clock with 2x Drive/Frequency Select 3.
3.3V 14.318-MHz clock
output. This pin also serves as the select strap to determines device operating
frequency as described in
Table 5.
Crystal Input.
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output.
An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
PCI Clock 0/Frequency Selection 0.
3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in
Table 5.
PCI Clock 1/Frequency Selection 1.
3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in
Table 5.
PCI Clock 2/Frequency Selection 2.
3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in
Table 5.
PCI Clock 3 through 7.
3.3V 33-MHz PCI clock outputs. PCI0:7 can be individ-
ually turned off via SMBus interface.
66-MHz Clock Output.
3.3V output clocks. The operating frequency is
controlled by FS0:4 (see
Table 5).
48MHz.
3.3V 48-MHz non-spread spectrum output.
48-MHz Output/Frequency Selection 4.
3.3V 48-MHz non-spread spectrum
output. This pin also serves as the select strap to determine device operating
frequency as described in
Table 5.
24- or 48-MHz Output/Select 24 or 48MHz.
3.3V 24 or 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the output
frequency for 24_48MHz output.
X1
X2
PCI0/FS0
4
5
11
I
O
I/O
PCI1/FS1
12
I/O
PCI2/FS2
13
I/O
PCI3:7
3V66_0:2
48MHz
48MHz/FS4
15, 16, 18, 19, 20
7, 8, 9
22
23
O
O
O
I/O
24_48MHz/SEL24
_48MHz#
RST#
24
I/O
30
Reset#.
Open-drain RESET# output.
O
(open-d
rain)
O
CPU Clock Outputs.
Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:4. Voltage swing is set by
VDDQ2.
SDRAM Clock Outputs.
3.3V outputs for SDRAM and chipset. The operating
frequency is controlled by FS0:4 (see
Table 5).
Synchronous APIC Clock Outputs.
Clock outputs running synchronous with
the PCI clock outputs. Voltage swing set by VDDQ2.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection.
Power supply for SDRAM output buffers, PCI output
buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
2.5V Power Connection.
Power supply for APIC and CPU output buffers.
Connect to 2.5V.
Ground Connections.
Connect all ground pins to the common system ground
plane.
CPU0:1
52, 51
SDRAM0:12,
49, 48, 47, 44,
43, 42, 41, 38,
37, 36, 35, 32, 31
55
26
29
2, 6, 17, 25, 28,
34, 40, 46
53, 56
1, 10, 14, 21, 27,
33, 39, 45, 50, 54
O
O
I/O
I
P
P
G
APIC
SDATA
SCLK
VDDQ3
VDDQ2
GND
Rev 1.0, November 20, 2006
Page 2 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
