ICS87972I
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of FRZ_CLK signal.To place an output in the freeze state, a logic
ICS87972I (Except QC0 and QFB) can be individually frozen “0” must be written to the respective freeze enable bit in the shift
(stopped in the logic “0” state) using a simple serial interface register.To unfreeze an output, a logic “1” must be written to the
to a 12 bit shift register. A serial interface was chosen to elimi- respective freeze enable bit. Outputs will not become enabled/
nate the need for each output to have its own Output Enable disabled until all 12 data bits are shifted into the shift register.
pin, which would dramatically increase pin count and package When all 12 data bits are shifted in the register, the next rising
cost. Common sources in a system that can be used to drive edge of FRZ_CLK will enable or disable the outputs. If the bit
the ICS87972I serial interface are FPGA’s and ASICs.
that is following the 12th bit in the register is a logic “0”, it is used
for the start bit of the next cycle; otherwise, the device will wait
and won’t start the next cycle until it sees a logic “0” bit. Freez-
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze ing and unfreezing of the output clock is synchronous (see the
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which timing diagram below).When going into a frozen state, the out-
can be frozen has its own freeze enable bit in the 12 bit shift put clock will go LOW at the time it would normally go LOW, and
register.The sequence is started by supplying a logic “0” start the freeze logic will keep the output low until unfrozen. Likewise,
bit followed by 12NRZ freeze enable bits. The period of each when coming out of the frozen state, the output will go HIGH
FRZ_DATA bit equals the period of the FRZ_CLK signal. The only when it would normally go HIGH.This logic, therefore, pre-
FRZ_DATA serial transmission should be timed so the ICS87972I vents runt pulses when going into and out of the frozen state.
can sample each FRZ_DATA bit with the rising edge of the
FRZ_DATA
QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
FRZ_CLK
FIGURE 2A. FREEZE DATA INPUT PROTOCOL
Qx FREEZE Internal
Qx Internal
Qx Out
FIGURE 2B. OUTPUT DISABLE TIMING
87972DYI
www.icst.com/products/hiperclocks.html
REV.D NOVEMBER 29, 2005
10
SPECTRUM [ SPECTRUM MICROWAVE, INC. ]
