PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889832
L
OW
S
KEW
, 1-
TO
-4 D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
F
EATURES
•
Four differential LVDS outputs
•
IN, nIN pair can accept the following differential input
levels: LVPECL, LVDS, SSTL
•
50Ω internal input termination to V
T
•
Output frequency: > 2GHz
•
Output skew: TBD
•
Part-to-part skew: TBD
•
Additive phase jitter, RMS: TBD
•
Propagation delay: 460ps (typical)
•
2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-complaint
packages
G
ENERAL
D
ESCRIPTION
The ICS889832 is a high speed 1-to-4 Differential-
to-LVDS Fanout Buffer and is a member of the
HiPerClockS™
HiPerClockS
™
family of high performance
clock solutions from ICS. The ICS889832 is
optimized for high speed and very low output
skew, making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and
Fibre Channel. The internally terminated differential input
and V
REF
_
AC
pin allow other differential signal families
such as LVPECL, LVDS, and SSTL to be easily interfaced
to the input with minimal use of external components. The
device also has an output enable pin which may be useful
for system test and debug purposes. The ICS889832 is
packaged in a small 3mm x 3mm 16-pin VFQFN package
which makes it ideal for use in space-constrained
applications.
IC
S
B
LOCK
D
IAGRAM
Q0
nQ0
IN
50Ω
P
IN
A
SSIGNMENT
Q1 1
nQ1 2
Q2 3
Q1
nQ1
nQ2 4
5
Q3
16 15 14 13
12
11
10
9
6
nQ3
GND
nQ0
V
DD
Q0
IN
V
T
V
REF
_
AC
nIN
7
V
DD
8
EN
V
T
50Ω
nIN
Q2
V
REF_AC
EN
D
Q
nQ2
ICS889832
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
889832AK
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 23, 2006