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SMCJ10 参数 Datasheet PDF下载

SMCJ10图片预览
型号: SMCJ10
PDF下载: 下载PDF文件 查看货源
内容描述: 瞬态电压抑制器 [Transient Voltage Suppressors]
分类和应用:
文件页数/大小: 4 页 / 726 K
品牌: SSC [ SILICON STANDARD CORP. ]
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SMCJ Series
Transient Voltage Suppressors
PRODUCT SUMMARY
Stand-off Voltage ratings from 5.0V to 440V
Peak pulse power 1500W in SMC surface-mount package
FEATURES
Plastic package has Underwriters Laboratory Flammability
Classification 94V-0
Low profile package with built-in strain relief for surface-mount
Glass passivated junction
Low incremental surge resistance, excellent clamping capability
Peak pulse power capability of 1500W with a 10/1000us waveform,
repetition rate (duty cycle): 0.01%
Very fast response time
High temperature soldering guaranteed:
260°C for 10 seconds at terminals
MECHANICAL DATA
Case: JEDEC DO-214AB (SMC) molded plastic over passivated chip
Terminals: Matte-Sn plated, solderable per MIL-STD-750,
Method 2026
Polarity: For uni-directional types the band denotes the cathode, which
is positive with respect to the anode under normal TVS operation.
Mounting position: Any
Weight: 0.007oz., 0.21g
Pb-free; RoHS-compliant
Devices for Bidirectional Applications
For bi-directional devices, use suffix CA (e.g. SMCJ10CA). Electrical characteristics apply in both directions.
MAXIMUM RATINGS
Rating at 25°C ambient temperature unless otherwise specified.
Parameter
Peak pulse power dissipation with
a 10/1000
u
s waveform
(1,2)
(see Fig. 1)
Peak pulse current with a 10/1000
u
s waveform
(1)
Peak forward surge current, 8.3ms single half sine-wave
uni-directional only
(2)
Typical thermal resistance, junction to ambient
(3)
Typical thermal resistance, junction to lead
Operating junction and storage temperature range
Symbol
P
PPM
I
PPM
I
FSM
R
θ
JA
R
θ
JL
T
J
, T
STG
Value
Minimum 1500
See Next Table
200
75
15
-55 to +150
Unit
W
A
A
°C/W
°C/W
°C
Notes:
1. Non-repetitive current pulse, per Fig. 3 and derated above TA=25°C per Fig. 2.
2. Mounted on 0.31" x 0.31" (8.0 mm x 8.0 mm) copper pads at each terminal
3. Mounted on minimum recommended pad layout
9/21/2006 Rev.4.01
www.SiliconStandard.com
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