3.3V
3.3V
3.3V
74LCX244
20
VCC
D1
D2
D3
D4
D5
R6
R7
R8
R5
R4
1OE
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
10
GND
U4
74LCX244
20
VCC
1OE
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
1
D6
D7
D8
2A1
2A2
2A3
2A4
10
GND
U5
JP9
1
3
1
3
2
2
1x3 HEADER
C3
0.1uf, 0603
C4
0.1uf, 0603
2Y1
2Y2
2Y3
2Y4
2OE
9
7
5
3
19
D9
D10
R9
R10
R11
R12
R13
120, 0603
120, 0603
120, 0603
120, 0603
1k, 0603
3.3V
2OE
19
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
1
1k, 0603
1k, 0603
1k, 0603
1k, 0603
1k, 0603
2.5V
JP1
2
VALTIME
E4
E5
E6
F4
F5
F6
5
SMC/S3N
8
DSBLFOS
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
RVRT
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
11
E7
E8
E9
F7
F8
F9
G4
G5
G6
G7
G8
H8
J8
K8
2
4
6
8
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
18
16
14
12
14
AUTOSEL
17
DSBLFSYNC
CLKIN_A+
CLKIN_A-
CLKIN_B+
CLKIN_B-
REF/CLKIN_F+
REF/CLKIN_F-
CLKIN_A+
CLKIN_A-
CLKIN_B+
CLKIN_B-
REF/CLKIN_F+
REF/CLKIN_F-
CLKOUT_1+
CLKOUT_1-
CLKOUT_2+
CLKOUT_2-
CLKOUT_3+
CLKOUT_3-
CLKOUT_4+
CLKOUT_4-
11
13
15
17
9
7
5
3
C2
C1
G1
G2
E2
E1
CLKOUT_1+
CLKOUT_1-
CLKOUT_2+
CLKOUT_2-
CLKOUT_3+
CLKOUT_3-
CLKOUT_4+
CLKOUT_4-
20
K4
K3
K6
K7
K10
K9
H10
G10
MANCNTRL[0]
23
U1
Si5364_revB
MANCNTRL[1]
26
FEC[0]
29
FEC[1]
32
BWSEL[0]
35
BWSEL[1]
38
FRQSEL_1[0]
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
FSYNC
2
4
6
8
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
18
16
14
12
F10
E10
D10
A5
A6
A7
A8
A9
A10
B10
J1
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
FSYNC
41
FRQSEL_1[1]
44
FRQSEL_2[0]
RES/DEV_ID[0]
RES/DEV_ID[1]
RES/DEV_ID[2]
RES/ANAOUT
11
13
15
17
B8
B7
B6
C6
RES/DEV_ID[0]
RES-DEV)ID[1]
REV/DEV_ID[2]
RES/ANAOUT
47
FRQSEL_2[1]
50
FRQSEL_3[0]
53
FRQSEL_3[1]
56
REXT
FRQSEL_4[0]
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
BWSEL[0]
BWSEL[1]
FEC[0]
FEC[1]
MANCNTRL[0]
MANCNTRL[1]
DSBLFSYNC
AUTOSEL
RVRT
RSTN/CAL
VALTIME
SMC/S3N
DSBLFOS
FXDDELAY
SYNCIN
INCDELAY
DECDELAY
VSEL33
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
BWSEL[0]
BWSEL[1]
FEC[0]
FEC[1]
MANCNTRL[0]
MANCNTRL[1]
DSBLFSYNC
AUTOSEL
RVRT
RSTN/CAL
VALTIME
SMC/S3N
DSBLFOS
FXDDELAY
SYNCIN
INCDELAY
DECDELAY
VSEL33
RES/TMODE[0]
RES/TMODE[1]
RES/TMODE[2]
RES/REFIN[0]
RES/REFIN[1]
RES/REFIN[2]
RES/PFDTEST
C9
C8
C7
D2
F1
F2
D1
RES/TMODE[0]
RES/TMODE[1]
RES/TMODE[2]
RES/REFIN[0]
RES/REFIN[1]
RES/REFIN[2]
RES/PFDTEST
J3
J4
J6
J7
J10
J9
G9
H9
A2
B2
A3
B3
A4
B4
H2
B1
C10
K2
J2
B9
B5
C5
H1
C3
C4
D3
FRQSEL_4[1]
1
3
4
6
7
9
10
12
13
15
16
18
19
21
22
24
25
27
28
30
31
33
34
36
37
39
40
42
43
45
46
48
49
51
52
54
55
57
58
60
61
63
R1
10k, 0603
3.3V
R29
0, 0402
1
3
SW3
101-0161
2
JP6
JP11
2
1
3
RSTN/CAL
3.3V
JP8
2
5
8
11
14
17
20
20
RES/PFDTEST
17
RES/REFIN[2]
14
RES/REFIN[1]
11
RES/REFIN[0]
8
RES/TMODE[2]
5
RES/TMODE[1]
4.99k, 0603
2
RES/TMODE[0]
1
3
5
7
2
4
6
8
RES/DEV_ID[0]
RES-DEV)ID[1]
REV/DEV_ID[2]
RES/ANAOUT
JP10
R28
JP2
1
3
1
3
2
2
SYNCIN
1x3 HEADER
JP3
1
3
1
3
2
2
VSEL33
Preliminary Rev. 0.33
1
3
4
6
7
9
10
12
13
15
16
18
19
21
1
3
4
6
7
9
10
12
13
15
16
18
19
21
7x3 HEADER
1x3 HEADER
For engineering test purposes only. Not
needed for customer application.
D4
D5
D6
D7
D8
D9
E3
F3
G3
H3
H4
H5
H6
H7
J5
K5
1
3
5
7
2
4
6
8
62
FXDDELAY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
59
K1
3.3V
3.3V
R26
0, 0402
1
3
1
3
JP4
101-0161
0.1uf, 0603
3
SW2
C2
2
INCDELAY
74SZ14
2
2
4
R3
100k, 0402
U7
5
1
3
R27
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
20
18
16
14
12
10
8
6
4
2
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
19
17
15
13
11
9
7
5
3
1
FSYNC
0, 0402
1
3
JP5
2
2
DECDELAY
1
2
JP15
R2
100k, 0402
U6
5
2
4
SW1
C1
3
74SZ14
101-0161
0.1uf, 0603
Si5364-EVB
Figure 1. Si5364-EVB Typical Application Schematic (page 1 of 2)
5
SSOUSA [ SOLID STATE OPTRONIC ]
