2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Data Sheet
PIN DESCRIPTION
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
1242 08-soic P1.0
3
Top View
6
4
5
1242 08-wson P2.0
8-
LEAD
SOIC
FIGURE 1: P
IN
A
SSIGNMENTS
TABLE 1: P
IN
D
ESCRIPTION
Symbol Pin Name
SCK
Serial Clock
Functions
8-
CONTACT
WSON
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
To provide power supply (3.0-3.6V).
T1.0 1242
SI
SO
CE#
WP#
HOLD#
V
DD
V
SS
Serial Data
Input
Serial Data
Output
Chip Enable
Write Protect
Hold
Power Supply
Ground
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
