4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
PIN DESCRIPTION
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
3
Top View
6
4
5
1295 08-soic S2A P1.0
1295 08-wson QA P2.0
8-Lead SOIC
FIGURE 2: Pin Assignments
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
8-Contact WSON
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See “Hardware End-of-Write Detection” on page 12 for details.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the
device.
To provide power supply voltage: 2.7-3.6V for SST25VF040B
T1.0 1295
SI
SO
Serial Data Input
Serial Data Output
CE#
WP#
HOLD#
V
DD
V
SS
Chip Enable
Write Protect
Hold
Power Supply
Ground
©2009 Silicon Storage Technology, Inc.
S71295-05-000
10/09
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
