8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
High-Speed-Read (66/80 MHz)
The High-Speed-Read instruction supporting up to 66 MHz
(for SST25VF080B-50-xx-xxxx) or 80 MHz (for
SST25VF040B-80-xx-xxxx) Read is initiated by executing
an 8-bit command, 0BH, followed by address bits [A23-A0]
and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 6 for
the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruc-
tion outputs the data starting from the specified address
location. The data output stream is continuous through all
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. Once the data from address
location FFFFFH has been read, the next output will be
from address location 00000H.
CE#
MODE 3
SCK
MODE 0
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SI
MSB
SO
0B
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
X
N
D
OUT
MSB
N+1
D
OUT
N+2
D
OUT
N+3
D
OUT
N+4
D
OUT
1296 HSRdSeq.0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
FIGURE 6: High-Speed-Read Sequence
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
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